1. Field of the Disclosure
The present disclosure relates generally to computing and memory devices and more particularly to multiple-die devices connected via an interposer.
2. Description of the Related Art
Communication and memory bandwidth and latency are significant bottlenecks in many processing systems. These performance factors may be improved to a degree by using die stacking techniques whereby multiple die implementing the processing system are disposed at a silicon substrate known as an interposer. The die may be stacked vertically using through-silicon vias (TSVs), or stacked horizontally using interconnects of the interposer, or a combination of both vertical stacking and horizontal stacking. In horizontal stacking, metal layers in the interposer typically are used to implement links to enable point-to-point communication between pairs of die. The use of point-to-point links to provide communication between horizontally-stacked die does not scale with the number of die. An increase in the number of die in a conventional horizontal-stacked system requires either an increase in the number of metal layers in the interposer, which significantly increases cost and complexity, or an increase in the lengths of certain traces of the interposer, which significantly increases power consumption, signal latency, and skew mismatch.
The use of the same reference symbols in different drawings indicates similar or identical items.